1 document # sram130 rev a revised september 2008 p3c1041 high speed 256k x 16 (4 meg) static cmos ram high speed (equal access and cycle times) ? 10/12/15/20 ns (commercial) ? 12/15/20 ns (industrial) low power ? 325 mw (max.) single 3.3v 0.3v power supply 2.0v data retention functional block diagram pin configuration 1519b features description the p3c1041 is a 262,144 words by 16 bits high-speed cmos static ram. the cmos memory requires no clocks or refreshing, and has equal access and cycle times. inputs are fully ttl-compatible. the ram oper- ates from a single 3.3v 0.3v tolerance power supply. access times as fast as 10 nanoseconds permit greatly enhanced system operating speeds. cmos is utilized to reduce power consumption to a low level. the p3c1041 is a member of a family of pace ram? products offer- ing fast access times. the p3c1041 device provides asynchronous operation with matching access and cycle times. memory loca- tions are specified on address pins a 0 to a 17 . reading is accomplished by device selection ( ce and output en- abling ( oe ) while write enable ( we ) remains high. by presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. the input/output pins stay in the high z state when either ce or oe is high or we is low. package options for the p3c1041 include 44-pin soj and tsop packages. easy memory expansion using ce ce ce ce ce and oe oe oe oe oe inputs fully ttl compatible inputs and outputs advanced cmos technology fast t oe automatic power down when deselected packages ?44-pin soj, tsop ii soj tsop ii
p3c1041 page 2 of 10 document # sram130 rev a maximum ratings (1) symbol parameter value unit v cc power supply pin with ?0.5 to +4.6 v respect to gnd terminal voltage with ?0.5 to v term respect to gnd v cc +0.5 v t a operating temperature ?55 to +125 c symbol parameter value unit t bias temperature under ?55 to +125 c bias t stg storage temperature ?65 to +150 c i out dc output current 20 ma recommended operating temperature and supply voltage i sb standby power supply current (ttl input levels) ce v ih v cc = max, f = max., outputs open v in v ih or v in v il ce v cc - 0.2v v cc = max, f = 0, outputs open v in v cc - 0.3v or v in 0.3v standby power supply current (cmos input levels) i sb1 industrial grade(2) ambient temperature gnd v cc 0v 0v 3.3v 0.3v 3.3v 0.3v symbol c in c out parameter input capacitance output capacitance conditions v in = 0v v out = 0v 8 8 unit pf pf capacitances (4) v cc = 3.3v, t a = 25c, f = 1.0mhz symbol dc electrical characteristics over recommended operating temperature and supply voltage (2) v ih i li i lo parameter input high voltage input low voltage input leakage current test conditions v cc = max. v in = gnd to v cc v cc = max., ce = v ih , v out = gnd to v cc typ. commercial ?40c to +85c 0c to +70c unit v v a a ma ma v ol output low voltage (ttl load) i ol = +8 ma, v cc = min. v output high voltage (ttl load) v oh i oh = ?4 ma, v cc = min. v output leakage current p3c1041 ___ 40 10 ___ min 2.0 ?0.3 (3) -1 -1 max v cc +0.3 0.8 +1 +1 0.4 2.4 v il
p3c1041 page 3 of 10 document # sram130 rev a *v cc = 3.6v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce = v il , oe = v ih . i cc symbol parameter temperature range dynamic operating current* commercial industrial n/a ?12 ?10 ?15 ?20 unit ma ma power dissipation characteristics vs. speed 90 85 95 80 90 75 85 ac electrical characteristics?read cycle (v cc = 3.3v 0.3v, all temperature ranges) (2) sym. t rc t aa t ac t oh t lz t hz t oe t olz t ohz t pu t pd parameter read cycle time address access time chip enable access time output hold from address change chip enable to output in low z chip disable to output in high z output enable low to low z output enable high to high z chip enable to power up time chip disable to power down time output enable low to data valid max min max min max min max min -10 -12 -15 -20 unit 10 3 3 0 0 10 10 5 5 5 10 12 3 3 0 0 12 12 6 6 6 12 15 3 3 0 0 15 15 7 7 7 15 20 3 3 0 0 20 20 8 8 8 20 ns ns ns ns ns ns ns ns ns ns ns t be byte enable to data valid 5 6 7 8ns t lzbe byte enable to low z 0 00 0 ns t hzbe byte disable to high z 6 6 7 8ns
p3c1041 page 4 of 10 document # sram130 rev a timing waveform of read cycle no. 2 ( oe oe oe oe oe controlled) (5,6) notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. transient inputs with v il not more negative than ?2.0v and v ih v cc + 0.5v, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. 5. we is high for read cycle. 6. ce is low and oe is low for read cycle. 7. address must be valid prior to, or coincident with ce transition low. 8. transition is measured 200 mv from steady state voltage prior to change, with loading as specified in figure 1. this parameter is sampled and not 100% tested. 9. read cycle time is measured from the last valid address to the first transitioning address. timing waveform of read cycle no. 1
p3c1041 page 5 of 10 document # sram130 rev a -10 ac characteristics?write cycle (v cc = 3.3v 0.3v, all temperature ranges) (2) sym. t wc t cw t as t wp t ah t dw t dh parameter write cycle time chip enable time to end of write address set-up time to write start write pulse width address hold time data hold time data valid to end of write max min max min max min max min -12 -15 -20 unit 10 0 7 0 12 0 8 0 15 0 10 0 20 0 10 0 7 7 0 5 8 8 0 6 10 10 0 7 10 10 0 8 ns ns ns ns ns ns ns ns t aw address valid to end of write write enable to output in high z t wz 56 7 8ns output active from end of write t ow 55 0 0ns timing waveform of write cycle no. 1 ( ce ce ce ce ce controlled) we high to low z t lzwe 33 3 3ns byte enable to end of write t bw 7 8 10 10 ns
p3c1041 page 6 of 10 document # sram130 rev a timing waveform of write cycle no. 2 ( ble ble ble ble ble or bhe bhe bhe bhe bhe controlled) timing waveform of write cycle no. 3 ( we we we we we controlled, oe oe oe oe oe low)
p3c1041 page 7 of 10 document # sram130 rev a input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 ac test conditions figure 1. output load figure 2. thevenin equivalent * including scope and test fixture. note: because of the ultra-high speed of the p3c1041, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal reflections, proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.73v (thevenin voltage) at the comparator input, and a 116 resistor must be used in series with d out to match 166 (thevenin resistance). active truth table standby power i/o 0 - i/o 7 we we we we we oe oe oe oe oe ce ce ce ce ce d out d out high z d in x h h h l x l l l x h l l l active active active high z l bhe bhe bhe bhe bhe ble ble ble ble ble x l h l l x l l h l i/o 8 - i/o 15 d out high z d out d in high z read upper bits only power-down mode read all bits read lower bits only write all bits d in l x l active h l high z write lower bits only high z l x l active l hd in write upper bits only high z h h l active x x high z selected, outputs disabled
p3c1041 page 8 of 10 document # sram130 rev a ordering information
p3c1041 page 9 of 10 document # sram130 rev a soj small outline ic package tsop ii thin small outline package pkg # # pins symbol min max a 0.128 0.148 a1 0.082 - b 0.013 0.023 c 0.007 0.013 d 1.120 1.130 e e 0.435 0.445 e1 0.395 0.405 e2 q0.025- j8 44 (400 mil) 0.050 bsc 0.370 bsc pkg # # pins symbol min max a 0.039 0.047 a 2 0.033 0.042 b 0.012 0.016 d 0.396 0.404 e 0.721 0.729 e h d 0.462 0.470 t2 44 0.0315 bsc
p3c1041 page 10 of 10 document # sram130 rev a revisions document number : sram130 document title : p3c1041 high speed 256k x 16 (4 meg) static cmos ram rev. issue date orig. of change description of change or oct-05 jdb new data sheet a sept-08 jdb updated tsop ii package drawing
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